A high-level modeling system (HLMS) allows a user to assemble, simulate, and debug an electronic circuit design. One example of an HLMS is the tool System Generator, produced by Xilinx, Inc.
An electronic circuit design in an HLMS is generally assembled from objects known as blocks. Each block performs a desired function in the design, and the blocks are connected to accomplish the overall function of the design. Some blocks, known as leaves, have no subblocks. Collections of leaves, called libraries, are often supplied to users as built-in parts of an HLMS. For example, several blocks representing various kinds of finite impulse response (FIR) filters are supplied in libraries that are part of System Generator. Other blocks, called non-leaves, are assembled by users and may have a hierarchy of sub-blocks. Non-leaves are constructed by grouping and connecting several blocks. The blocks that are collected in a non-leaf may be leaves or non-leaves.
HLMSs usually translate designs into electronic hardware. Many times this hardware is expressed using a hardware definition language (HDL) such as VHDL or Verilog. A design in VHDL (or comparably, Verilog) consists of objects called entities (modules in Verilog). Entities are generally low-level HDL equivalents to HLMS blocks. A basic approach to translating an HLMS design produces at least one entity per block, and sometimes more. Since an HLMS design can contain tens or even hundreds of thousands of blocks, many entities may be generated.
The HDL generated by an HLMS is processed by downstream tools such as synthesis compilers, HDL simulators, and design browsers. The amount of memory and processing time needed by a downstream tool are directly related to the number of entities compiled. Also, users of an HLMS may want to examine the generated HDL directly. When the HDL contains many entities, it can be nearly impossible for a user to understand.